At the present time, MOS circuits of field-effect transistors generally comprise polysilicon gates or gate structures which are constructed from a plurality of layers arranged one above the other, such as, for example, polysilicon/tungsten silicide or polysilicon/tungsten nitride/tungsten. However, such gates with a polysilicon layer at the interface with the gate oxide have quite a number of disadvantages, e.g., a high gate bulk resistance, dopant depletion in the polysilicon at the interface with the gate oxide, an increased dopant concentration permeating through the gate oxide in the channel, and an unfavorable value with regard to the work function. In order to simultaneously achieve a high performance both for the n-channel transistor and for the p-channel transistor, it is necessary to dope the polysilicon differently for the n-channel and p-channel transistors (dual work function).
If, in contrast to this, avoiding the above disadvantages, a metal is used as gate electrode, the problem arises that it is not possible to effect a patterning of the then metallic gate electrode selectively with respect to the gate oxide and a reoxidation of the gate, i.e., an encapsulation of the gate, with a thermal oxide, as in the case of an above processing of a polysilicon gate. Further, during the etching of metals the selectivity with respect to the oxide is significantly poorer than in the case of a poly gate, i.e., after a patterning of a metal layer, it is not possible to stop the etching operation within the underlying oxide layer, rather an incipient etching of the substrate in the overetching phase is unavoidable. This can lead to failure of the component.
Moreover, customary polysilicon gates and gates with a plurality of layers have high gate thicknesses in order to keep the sheet resistance sufficiently low. In the context of advancing miniaturization of the feature sizes, however, it is necessary also to reduce the gate stack height in order to be able to provide sufficiently large process windows for further process steps, such as an inclined implantation, for example. What is additionally problematic is the fabrication of gates with different work functions (dual work function gates) in circuits with a high performance requirement, which entails a high process complexity.